Recently, as display devices, liquid crystal display (LCD) devices that feature thinness, lightweight, lower power dissipation have been widespread used, and have been extensively utilized as display units of mobile devices including portable telephone apparatuses (such as mobile phones or cellular phones), PDAs (personal digital assistants), and notebook PCs. Recently, however, a technology for supporting a larger screen and a moving image of the liquid crystal display devices has been developed. Then, realization of tabletop large-screen display devices and tabletop large-screen liquid crystal TVs as well as display devices and TVs for mobile use have become possible. As these liquid crystal display devices, an active matrix driving system liquid crystal display device capable of performing high-definition display is employed. Referring to FIG. 9, a typical configuration of the active matrix driving system liquid crystal display device will be outlined. FIG. 9 schematically shows a main configuration connected to one pixel in a liquid crystal display unit, using an equivalent circuit.
Generally, a display unit 960 of the active matrix driving liquid crystal display device includes a semiconductor substrate, an opposing substrate, and a liquid crystal sealed in between these two substrates by opposing these two substrates. On the semiconductor substrate, there are arranged transparent pixel electrodes 964 and a thin film transistor (TFT) 963 in a matrix form (for example, for a color SXGA panel, 1280×3 pixel columns×1024 pixel rows).
Turning on and off of a TFT 963 having a switching function is controlled by a scan signal. When the TFT 963 is turned on, a gray scale voltage corresponding to a video signal is applied to a corresponding pixel electrode 964. Transmittance of the liquid crystal is changed by a potential difference between each pixel electrode 964 and the opposing substrate electrode 966, and the potential difference is held by a liquid crystal capacitance 965 for a certain period, thereby displaying an image. On the semiconductor substrate, transparent pixel electrodes 964 and thin-film transistors (TFTs) 963 are arranged in a matrix form (of 1280×3 pixel rows×1024 pixel columns in the case of a color SXGA panel, for example). One transparent electrode 966 is formed on an entire surface of the opposing substrate.
On the semiconductor substrate, data lines 962 and scan lines 961 are wired in the form of a grid (in which 1280×3 data lines and 1024 scan lines are arranged in the case of the color SXGA panel described above). A data line 962 sends a plurality of level voltages (gray scale voltages) applied to each pixel electrode 964, and a scan line 961 sends the scan signal. Due to a capacitance produced at an intersection between each of the scan lines 961 and each of the data lines 962 and a liquid crystal capacitance sandwiched between the semiconductor substrate and the opposing substrate, the scan lines 961 and the data lines 962 each have become a large capacitive load.
The scan signal is supplied to a scan line 961 from a gate driver 970, and a gray scale voltage is applied to each pixel electrode 964 from a data driver 980 through a data line 962. The gate driver 970 and the data driver 980 are controlled by a display controller 950. The necessary clock CLK, control signals, and the like, are respectively supplied by the display controller 950, and image data is supplied to the data driver 980. At present, digital data is predominantly used for image data.
Rewriting of data of one screen is usually performed in one frame period (of approximately 1/60 seconds). Data is successively selected every pixel row (every line) by each scan line, and a gray scale voltage is supplied from each data line within a selection period.
While the gate driver 970 should supply the scan signal of at least two values, the data driver 980 needs to drive a data line by the gray scale voltage of multi-valued levels corresponding to the number of gray scales. For this reason, the data driver 980 includes digital-to-analog conversion circuit which includes a digital-to-analog converter (DAC) for converting image data to grayscale signal voltage, and an amplifier circuit which amplifies and outputs to the data lines 962 the grayscale signal voltage.
Recently, image quality of liquid crystal display devices has been improved (or the number of colors used in the liquid crystal display devices has been increased). There has been a growing demand for at least 260 thousand colors (video data of six bits for each of colors of R, G, B) and 26,800 thousand colors (video data of eight bits for each of the colors of R, G, B) or more. For this reason, in data drivers which output grayscale signal voltage corresponding to multi-bit image data, the circuit scale of the DAC increases, and as a result, the chip area of a data driver LSI increases, which is a factor that leads to high cost. In addition as high resolution of liquid crystal display devices advances together with larger screens, load capacitance of the data lines 962 increases considerably, and 1 data selection period (1-data output period), which is approximately equivalent to 1 frame period divided by number of gate lines, becomes shorter. An amplifier circuit serving as an output buffer of a driver LSI chip must drive a large capacitive load at high speed with a high voltage accuracy in a short 1-data selection period.
As a low area DAC that converts multi-bit digital data into an analog voltage signal, a serial DAC is known in which a reference voltage is sequentially sampled according to digital data inputted in a time-serial manner, and level voltages are obtained by repeating charge distribution among capacitors.
FIG. 10 is a diagram showing an example of a configuration of a digital-to-analog conversion circuit provided with a serial DAC described in Patent Document 1, mentioned below. Meanwhile, the present specification, a circuit block that converts a digital signal into an analog signal is denoted as a DAC (Digital-to-Analog Converter), and is distinguished from a configuration which includes a DAC and an amplifier circuit that amplifies an output of the DAC, which is denoted as a digital-to-analog conversion circuit.
The digital-to-analog conversion circuit of FIG. 10 includes a serial DAC that includes voltage supply terminals N5 and N6 supplied with two reference voltages V5 and V6, respectively, a capacitor C91 that has a first terminal connected to the voltage supply terminal N5, and a second terminal connected to a terminal N51, a capacitor C92 that has a first terminal connected to the voltage supply terminal N5, and a second terminal connected to a terminal N52, a changeover switch 911 that switches connection of the terminal 51 to the voltage supply terminal N5 or N6, a switch 912 that is connected between the terminal N51 and N52, a switch 913 that is connected between the terminal N52 and the voltage supply terminal N5, and a voltage follower circuit 919 that is composed by a differential amplifier which has a non-inverting input end (+) and an inverting input end (−) connected to the terminal N52 and an output terminal, respectively. Meanwhile, capacitance values of the capacitors C91 and C92 are normally configured to be equal.
The operation of the digital-to-analog conversion circuit of FIG. 10 will now be described. First, the switch 913 is temporarily turned ON, and potential difference (inter-terminal voltage) between the two ends (N5 and N52) of the capacitor C92 is reset to zero.
Next, either of the reference voltages V5 or V6 is sampled at the terminal N51 by the changeover switch 911, in accordance with a value of lowest bit data B1 of digital data (B1-BK) received in a time serial manner, and then after, the changeover switch 911 is turned OFF (open). The switch 912 is turned ON and charge redistribution occurs between the capacitors C91 and C92. Then the switch 912 is turned OFF and the charge is held in the capacitor C92.
Continuing to this, either of the reference voltages V5 or V6 is sampled at the terminal N51 by the changeover switch 911, according to next bit data B2, and after charge redistribution occurs between the capacitors C91 and C92 by the switch 912, the redistributed charge is held in the capacitor C92.
In the same way, sample and hold operations are repeated in order from lower bit data to higher bit data.
In cases of K bit data, one cycle of sampling and holding is repeated K times, and the voltage of the terminal N52 at this time is expressed by the following formula (1).VN52=(2−1×BK+2−2×BK-1+ . . . +2−K×B1)×(V6−V5)+V5  (1)where BK, BK-1, . . . , B1 are 0 or 1.
Voltage VN52 is amplified and outputted as Vout by the voltage follower circuit 919. In this way, the digital-to-analog conversion circuit of FIG. 10 can output each voltage level obtained by dividing an interval between the reference voltage V5 and V6 equally into 2K, in accordance with K bit data.
The digital-to-analog conversion circuit of FIG. 10 is featured in that, since the number of elements does not depend on the number of bits of the data, circuit size can be made very small (area saving) for the configuration of large number of bits.
However, the output voltage of the digital-to-analog conversion circuit of FIG. 10, is a liner in which voltage levels each are equally spaced, and with such, it is not possible to output a grayscale voltage matching the non-linear gamma characteristic of liquid crystal.
In this regard, recently in Non-Patent Document 1, there is disclosed a method of configuring a DAC to enable linear output several times the number of grayscale voltages necessary for output, and, among multiple linear output levels thereof, grayscale voltages matching the non-linear gamma characteristic of liquid crystal are allocated.
In this method, the number of bits corresponding to the number of grayscale voltages actually outputted is increased by approximately 2 or 3 bits. Therefore, the digital-to-analog conversion circuit as in FIG. 10 which does not depend on the number of bits is preferable.
[Patent Document 1]
JP Patent Kokai Publication No. JP-A-59-154820A (FIG. 1)
[Non Patent Document 1]
SOCIETY FOR INFORMATION DISPLAY 2004 INTERNATIONAL SYMPOSIUM DIGEST OF TECHNICAL PAPERS VOLUME XXXV pp. 1556-1559
[Non Patent Document 2]
IEEE JOURNAL OF SOLID-STATE CIRCUITS, VOL. 40, NO. 12, DECEMBER 2005, pp. 2756-2765